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ASEE-SE Annual Conference 2022

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Final Paper
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Synthesis Vs. Simulation: Developing A Hardware Interrupt System For The Instructional Processor

An Instructional Processor has been developed as a design example in an Advanced Digital Systems course. The architecture is modelled in VHDL and can be simulated using Xilinx design tools. A basic microcontroller is created by adding memory-mapped input/output. The system is synthesized and implemented in hardware on an FPGA. The goal of this project was to add a hardware interrupt system to the Instructional Processor. The enhanced microcontroller was then interfaced with multiple peripheral devices.

A hardware interrupt is a signal sent by a device requesting attention of the processor. The current program is temporarily suspended to service the request. An interrupt system was developed for the Instructional Processor including a hardware timer and a serial UART. The design process highlighted several important differences between what can be demonstrated via simulation and what can be synthesized to actual hardware.

The enhanced FPGA microcontroller was tested using a time-multiplexed display and a serial RFID card reader. This design example gives students an in-depth look at both the internal details and external interfacing of a real-life system. Challenges were also presented in programming multi-tasking software to service independent hardware interrupt requests. The hardware/software system is able to demonstrate reading and displaying of the tag ids.

This project successfully implemented a hardware interrupt system for the Instructional Processor. Valuable insights were gained highlighting subtle differences in simulation results vs. synthesis to actual hardware. The expanded processor design example has been added to a graduate Computer Architecture course, which uses VHDL and Xilinx FPGAs. The ever-evolving project continues to achieve its goal as a valuable instructional tool for the Computer Engineering curriculum.

Ronald Hayne
The Citadel
United States


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